Job Description:
Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.
Minimum Qualifications:
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field with 2+ Years of experience in Physical Design execution.
- Deep knowledge in RTL-to-GDS workflows, including synthesis, place and route, and static timing analysis.
- Expertise in optimization techniques for power, performance, and area (PPA).
- Hands-on experience with industry-standard EDA tools for physical design and verification.
- Comprehensive knowledge of clock tree synthesis and low-power design techniques.
- Experience with competitive timing, floor planning methodologies (TFM), and multi-power domain analysis.
Preferred Qualifications:
- Demonstrated ability to collaborate within cross-functional teams to achieve strategic design goals.
- Strong critical thinking and problem-solving skills to manage complex design challenges.
- Excellent communication and organizational abilities to coordinate across disciplines.
- A passion for innovation and continuous improvement in design methodologies.